TWI on ATxmega128A1 as master signals "bus error" in status flag, although the bus looks fine. After writing the address (read slave) I receive an ACK from the client. I can verify this on oszilloscope. Unfortunately the chip sets the "bus error" flag in status register on raising the WIF interrupt. According to datasheet the chip cannot find multiple of 9 bits between start and stop condition for setting the error. But there is neither a stop nor a repeated start condition on oszilloscope. I simply expect the slave to answer on masters clock, but the atmel signals error. I cannot find why. The parallel I2C sniffer (beagle) cannot find a problem as well, except that the remaining data on bus is missing (because of the error flag set and my software stops the transaction). Did anyone found a similar behavior?
Thx
Thx
