Habe jetzt mal ein bischen tiefer geforscht...
Bei dem lesen läuft auch schon was falsch...
Hier zu sehen ist die Routine zum lesen der Mifare x Karten ->
CodeBox C
[I]uint8_t[/I] mfrc522_read_block([I]uint8_t[/I] blockAddr, [I]uint8_t[/I] *recvData)
{
[I]uint8_t[/I] status;
[I]uint32_t[/I] unLen;
recvData[0] = PICC_READ;
recvData[1] = blockAddr;
mfrc522_calculateCRC(recvData,2, &recvData[2]);
status = mfrc522_to_card(PCD_TRANSCEIVE, recvData, 4, recvData, &unLen);
char Buffer[20];
[I]sprintf[/I](Buffer,"unLen = %"[I]PRIu32[/I],unLen);
uart_puts(Buffer);
uart_puts("\r\n");
if ((status != CARD_FOUND) || (unLen != 0x90)) // 0x90 = 144
{
status = ERROR;
}
return status;
}
Bei der Variablen "unLen" bekomme ich ständig nur eine 0x04 zurück. Das heißt irgendwas läuft total falsch... Bloß was?
Hier ist die Funktion die die komplette Kommunikation mit dem Chip handelt... Vill. weiß einer von euch, was falsch läuft?
CodeBox C
/*
send command to rc522 to card
*/
[I]uint8_t[/I] mfrc522_to_card([I]uint8_t[/I] cmd, [I]uint8_t[/I] *send_data, [I]uint8_t[/I] send_data_len, [I]uint8_t[/I] *back_data, [I]uint32_t[/I] *back_data_len)
{
[I]uint8_t[/I] status = ERROR;
[I]uint8_t[/I] irqEn = 0x00;
[I]uint8_t[/I] waitIRq = 0x00;
[I]uint8_t[/I] lastBits = 0;
[I]uint8_t[/I] n = 0;
[I]uint8_t[/I] tmp = 0;
[I]uint32_t[/I] i = 0;
switch (cmd)
{
case MFAuthent_CMD: //Certification cards close
{
irqEn = 0x12;
waitIRq = 0x10;
break;
}
case Transceive_CMD: //Transmit FIFO data
{
irqEn = 0x77;
waitIRq = 0x30;
break;
}
default:
break;
}
//mfrc522_write(ComIEnReg, irqEn|0x80); //Interrupt request
n=mfrc522_read(ComIrqReg);
mfrc522_write(ComIrqReg,n&(~0x80));//clear all interrupt bits
n=mfrc522_read(FIFOLevelReg);
mfrc522_write(FIFOLevelReg,n|0x80);//flush FIFO data
mfrc522_write(CommandReg, Idle_CMD); //NO action; Cancel the current cmd???
//Writing data to the FIFO
for (i=0; i<send_data_len; i++)
{
mfrc522_write(FIFODataReg, send_data[i]);
}
//Execute the cmd
mfrc522_write(CommandReg, cmd);
if (cmd == Transceive_CMD)
{
n=mfrc522_read(BitFramingReg);
mfrc522_write(BitFramingReg,n|0x80);
}
//Waiting to receive data to complete
i = 2000; //i according to the clock frequency adjustment, the operator M1 card maximum waiting time 25ms???
do
{
//CommIrqReg[7..0]
//Set1 TxIRq RxIRq IdleIRq HiAlerIRq LoAlertIRq ErrIRq TimerIRq
n = mfrc522_read(ComIrqReg);
i--;
}
while ((i!=0) && !(n&0x01) && !(n&waitIRq));
tmp=mfrc522_read(BitFramingReg);
mfrc522_write(BitFramingReg,tmp&(~0x80));
if (i != 0)
{
if(!(mfrc522_read(ErrorReg) & 0x1B)) //BufferOvfl Collerr CRCErr ProtecolErr
{
status = CARD_FOUND;
if (n & irqEn & 0x01)
{
status = CARD_NOT_FOUND; //??
}
if (cmd == Transceive_CMD)
{
n = mfrc522_read(FIFOLevelReg);
lastBits = mfrc522_read(ControlReg) & 0x07;
if (lastBits)
{
*back_data_len = ([I]uint32_t[/I])(n-1)*8 + ([I]uint32_t[/I])lastBits;
}
else
{
*back_data_len = ([I]uint32_t[/I])n*8;
}
if (n == 0)
{
n = 1;
}
if (n > MAX_LEN)
{
n = MAX_LEN;
}
//Reading the received data in FIFO
for (i=0; i<n; i++)
{
back_data[i] = mfrc522_read(FIFODataReg);
}
}
}
else
{
status = ERROR;
}
}
//mfrc522_setBitMask(ControlReg,0x80); //timer stops
//mfrc522_write(CommandReg, PCD_IDLE);
return status;
}
